Title:PIC18f4520 Features
40 PIN PDIP
Oscillator configuration:
Features:
Wide operating voltage range : 2.0v to
5.5v
Sink/source current per
I/O :
25mA
Operating Frequency:
External
-To external RC modes(upto 4Mhz)
-Two external clock modes(upto 40Mhz)
Internal
-8 user selectable frequency from 31khz to 8Mhz
Resets : POR(Power
on reset), BOR(Brown Out reset)
Program memory(Flash) :
32 KB (32768 bytes)
Data memory : 1536
bytes
EEPROM data Memory : 256 bytes
I/O ports
:
A,B,C,D,E (A-8Pins)(b-8Pins) (C-8Pins)(D-8Pins) (E-4Pins)
Timers: 4 Timers
-T0 = 8,16 bits
-T1 = 8,16 bits
-T2 = 8 bits
-T3 = 8,16 bits
Capture/Compare/PWM : 1 CCP
Interrupts : 20
Digital communication peripherals :
-MSSP
(I2C,SPI)
-USART
Parallel communication : PSP(parallel slave port)
Parallel communication : PSP(parallel slave port)
Analog to Digital converter : (ADC) 13 Channels ,
each 10 bit
Analog Comparators : 2
Instruction Set : 75 Instruction ,83 with extended Instruction set
enabled
Packages : 40 PIN PDIP(plastic dual inline package)
44 PIN QFP(quad flat package)
44 PIN TQFP(thin quad flat
package)
40 PIN PDIP
Oscillator configuration:
1.Crystal Oscillator/Ceramic Resonators mode:
In
XT, LP, HS or HSPLL Oscillator modes, a crystal or ceramic resonator is
connected to the OSC1 and OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections.
2.RC oscillator mode:
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on theOSC2pin. This signal may be used for
test purposes or to
synchronize other logic.
Resets:
Power on reset:
A Power-on Reset pulse is generated on-chip whenever VDD
rises above a certain threshold. This allows the device
to start in the
initialized state when VDD is adequate for operation.
Brown out reset:
The BOR threshold is
set by the BORV1:BORV0 bits. If BOR is enabled (any values of
BOREN1:BOREN0,except ‘00’), any drop of VDD below VBOR for greater than TBOR will reset the device.
A Reset may or may not occur if VDD falls below VBOR for less than TBOR. The
chip will remain in Brown-out Reset until VDD rises above VBOR.
If the Power-up Timer
is enabled, it will be invoked after .VDD rises above VBOR; it then will keep
the chip in Reset for an additional time delay.
For Basic Electronics Kindaly follow this Link:
http://basicelectonicspalakpatel.blogspot.in/2014/08/the-mosfet-as-switch.html
For Basic Electronics Kindaly follow this Link:
http://basicelectonicspalakpatel.blogspot.in/2014/08/the-mosfet-as-switch.html
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